The present invention relates to a demodulation clock generator circuit. More particularly it relates to a demodulation clock generator circuit to be employed in a modulation system such as a bi-phase mark system in which a so-called self clock is enabled.
A demodulation clock generator has been employed in various fields of modern electronics, especially for electronics utilizing digital technology. One example of a data signal to be demodulated is shown in FIG. 4, namely, a digital audio interface signal modulated by a bi-phase mark modulation system. One sub-frame consists of 32 time slots. Time slots 0 through 3 are used for a preamble portion whose waveform corresponds to a sub-frame synchronization pattern containing predetermined bit patterns. Time slots 4 through 31 are used for a data portion of digital audio signals which are modulated by a bi-phase mark modulation system. Each time slot corresponds to symbols containing two continuous binary digits. In the data portion, the state of the first symbol of each time slot is always different from the state of the second symbol of the time slot immediately preceding that slot. The state of the second symbol of each time slot is the same as the state of the first symbol of the same slot when the value of the data bit corresponding to the time slot is "0", and the state of the second symbol of each time slot is different from that of the first symbol when the value of the data bit corresponding to the time slot is "1".
In FIGS. 5A to 5C, three different samples of synchronization patterns of the preamble portion of sub-frame contain bit patterns which do not appear in the data portion of the sub-frame.
Digital audio interface data signals modulated by the bi-phase mark modulation system contain signal components whose frequencies are equal to one time slot and whose frequencies are equal to one half of one time slot.
Hereinafter, one example of a circuit for a demodulation clock generator in the prior art technology for digital audio interface data signals which are modulated by a bi-phase mark system will be explained according to the illustration shown in FIG. 6. In the Figure, data signals to be demodulated are supplied to a demodulator 1 and a reference pulse generator 2. Reference pulse generator 2 creates two pulses by differential operation of the data signal to be demodulated. One of these pulses is synchronized to the leading edge of the data signal to be demodulated and the other is synchronized to the trailing edge of the data signal. One of these pulses is selected and its period is made longer than a predetermined value, and is output as a reference. The reference pulse generator 2 can be constructed, for example, using the following devices:
(a) a differential circuit by which two series of pulses as shown in FIG. 7 at (B) and (C) are generated synchronous with the leading edge and the trailing edge, respectively, of the data signal to be demodulated as shown in FIG. 7 at (A);
(b) a monostable multivibrator which is triggered at the trailing edge of the series of pulses and which produces an output pulse having a duration of a little less than one time slot;
(c) a gate circuit which outputs the pulse signal of the series of pulses only when the output pulse of the monostable multivibrator is present, thereby to produce a reference signal as shown in FIG. 7 at (D).
The reference signal output from reference pulse generator 2 is supplied to a phase locked loop (PLL) circuit 3. In PLL circuit 3, the reference signal is applied to a phase comparator 4 for comparing the phase with an output signal from a frequency divider 5. In the phase comparator, a signal corresponding to the phase difference between the reference signal and the output signal from the frequency divider 5 is output. This phase difference signal is supplied to a voltage-controlled oscillator (hereinafter referred to as VCO) 7 as an input voltage after passing through a low pass filter (hereinafter referred to as LPF) 6. The output signal from VCO 7 is supplied to frequency divider 5 to be divided by a ratio of, for example, one-sixth. The output signal from frequency divider 5 is simultaneously supplied to phase comparator 4 and to demodulator 1 as a clock signal for demodulation. Thus, the demodulation of the modulated signal is attained.
In the above-described example of a demodulation clock generator, the frequency of the signal supplied from reference pulse generator 2 is not always fixed to a determined value. Therefore, it takes a long time to set up the overall circuit after the data signal to be demodulated has first been supplied. This process will be explained further with the illustration of FIG. 8. In FIG. 8, the horizontal axis represents time and the vertical axis represents the oscillating frequency of VCO 7.
VCO 7 oscillates at a predetermined self-oscillation frequency f.sub.A. The bits of the data signal to be demodulated are all "0" at time t.sub.1 and the component of the signal having a frequency corresponding to a period of two time slots becomes larger. Due to this change, the demodulation clock signal output from frequency divider 5 becomes synchronized with the frequency corresponding to a period of one-half of a time slot and the frequency of VCO 7 becomes one-half of the predetermined frequency (f.sub.0 /2) at time t.sub.2. When a data signal consists of "0" and "1" at time t.sub.3, the level of the signal component having a frequency corresponding to a period of a full time slot of the data signal to be demodulated becomes higher and the frequency of the output signal from VCO 7 is correctly adjusted to the same value as the predetermined value (f.sub.0) at time t.sub.4. Thus, the process of setting up the overall circuit has been completed.
As described above, in a circuit for producing a demodulation clock signal using the prior art technique, the set-up process is not completed until the data input bits consist of "0" and "1". Because of this fact, a correct demodulating process cannot be attained correctly for a long period of time after the data signal to be demodulated has been supplied.